1. Field of the Invention
This invention relates to a semiconductor device and, more particularly, to a semiconductor device having a memory that includes cells in need of refresh for data retention.
2. Description of Related Art
In a DRAM (Dynamic Random-Access Memory) provided with redundant cells for rescuing faulty cells, a faulty cell detected by for example a wafer test, is replaced with a redundant cell. More specifically, a word line of a faulty cell is replaced with a redundant word line in a redundancy area by fuse programming (fuse blowing) of a redundancy decoder circuit. As a result, when an X address (row address) to be accessed matches an X address of the faulty cell, a redundancy decoder circuit selects a redundant word line in the redundancy area based upon the fuse-programmed information and accesses the redundant word line instead of the word line of the faulty cell.
As an example of the related art, Patent Document 1 (JP Patent Kokai Publication No. 05-342859) describes an arrangement having a circuit for receiving a test mode signal, exercising control in such a manner that only higher-order bits (nine higher-order bits) higher than a specific bit of the output signal of a refresh address counter are fixed at the same level, and exercising control in such a manner that lower-order bits (two lower-order bits) are changed by counter operation, wherein when a CBR(CAS before RAS) cycle is executed, higher-order bits (nine higher-order bits) of an internal row address are fixed at HIGH, only lower-order bits are changed and only some word lines are selected. As an example of manipulating bit position, Patent Document 2 discloses an arrangement in which an address generator for FFT (Fast-Fourier Transform) computation includes a rearranging unit in which the order of bits from the most significant bit to the least significant bit of a parallel register is reversed. With regard to a test of a redundancy arrangement, see the description of Patent Document 3, etc.
[Patent Document 1]
JP Patent Kokai Publication No. JP-A-05-342859
[Patent Document 2]
JP Patent Kokai Publication No. JP-A-05-266059
[Patent Document 3]
JP Patent Kokai Publication No. JP-A-05-210998